School: Engineering

This unit information may be updated and amended immediately prior to semester. To ensure you have the correct outline, please check it again at the beginning of semester.

Your unit may be subject to government or third party COVID-19 vaccination requirements. Please consider this before enrolling in this unit, and speak with the unit coordinator if this raises any concerns.

  • Unit Title

    Digital Electronics
  • Unit Code

    ENS2456
  • Year

    2022
  • Enrolment Period

    1
  • Version

    2
  • Credit Points

    15
  • Full Year Unit

    N
  • Mode of Delivery

    On Campus
    Online
  • Unit Coordinator

    Dr Yamaan Esmiel Majeed AL-SHAMMARI

Description

This unit presents a technology review of digital logic families. Memory functions, memory types, and the design of large memory arrays are explained and an introduction to FPGA and CPLB programmable logic devices is given. Digital design and analysis methods, top-down design, algorithmic state machines (ASM), synthesis of ASM, sequencing and control and CPU design are also covered. An introduction to VHDL, simulation and testing of digital systems is included.

Prerequisite Rule

Students must pass 1 unit from ENS1161, ENS1162

Equivalent Rule

Unit was previously coded ENS2256

Learning Outcomes

On completion of this unit students should be able to:

  1. Analyse and design simple CPU.
  2. Describe digital logic in VHDL language.
  3. Describe digital systems as algorithmic state machines and synthesize ASM.
  4. Design a test for digital system.
  5. Use modern engineering design environment.
  6. Use the building blocks of digital systems, including programmable logic devices.

Unit Content

  1. Algorithmic state machines (ASM); synthesis of ASM.
  2. Digital design and analysis methods; top-down design.
  3. Digital logic families technology review.
  4. Engineering design environment.
  5. Introduction to VHDL.
  6. Memory as major component of digital systems memory types, large memory arrays.
  7. Programmable logic devices FPGA, CPLB.
  8. Sequencing and control; design of CPU.
  9. Simulation and testing of digital systems.
  10. VHDL description of combinational and sequential logic.

Learning Experience

ON-CAMPUS

Students will attend on campus classes as well as engage in learning activities through ECU's LMS

JoondalupMount LawleySouth West (Bunbury)
Semester 113 x 2 hour labNot OfferedNot Offered
Semester 113 x 2 hour lectureNot OfferedNot Offered
Semester 113 x 1 hour tutorialNot OfferedNot Offered

For more information see the Semester Timetable

ONLINE

Students will engage in learning experiences via ECU’s LMS as well as additional ECU learning technologies

Assessment

GS1 GRADING SCHEMA 1 Used for standard coursework units

Students please note: The marks and grades received by students on assessments may be subject to further moderation. All marks and grades are to be considered provisional until endorsed by the relevant School Progression Panel.

ON CAMPUS
TypeDescriptionValue
TestIn class tests30%
ReportLaboratory reports20%
Examination ^End of semester examination50%
ONLINE
TypeDescriptionValue
AssignmentOpen book take home test with viva component30%
ReportVirtual laboratory reports20%
Assignment ^Summative assessment of unit content50%

^ Mandatory to Pass


Disability Standards for Education (Commonwealth 2005)

For the purposes of considering a request for Reasonable Adjustments under the Disability Standards for Education (Commonwealth 2005), inherent requirements for this subject are articulated in the Unit Description, Learning Outcomes and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the support for students with disabilities or medical conditions can be found at the Access and Inclusion website.

Academic Integrity

Integrity is a core value at Edith Cowan University, and it is expected that ECU students complete their assessment tasks honestly and with acknowledgement of other people's work. This means that assessment tasks must be completed individually (unless it is an authorised group assessment task) and any sources used must be referenced.

Breaches of academic integrity can include:

Plagiarism

Copying the words, ideas or creative works of other people, without referencing in accordance with stated University requirements. Students need to seek approval from the Unit Coordinator within the first week of study if they intend to use some of their previous work in an assessment task (self-plagiarism).

Unauthorised collaboration (collusion)

Working with other students and submitting the same or substantially similar work or portions of work when an individual submission was required. This includes students knowingly providing others with copies of their own work to use in the same or similar assessment task(s).

Contract cheating

Organising a friend, a family member, another student or an external person or organisation (e.g. through an online website) to complete or substantially edit or refine part or all of an assessment task(s) on their behalf.

Cheating in an exam

Using or having access to unauthorised materials in an exam or test.

Serious outcomes may be imposed if a student is found to have committed one of these breaches, up to and including expulsion from the University for repeated or serious acts.

ECU's policies and more information about academic integrity can be found on the student academic integrity website.

All commencing ECU students are required to complete the Academic Integrity Module.

Assessment Extension

In some circumstances, Students may apply to their Unit Coordinator to extend the due date of their Assessment Task(s) in accordance with ECU's Assessment, Examination and Moderation Procedures - for more information visit https://askus2.ecu.edu.au/s/article/000001386.

Special Consideration

Students may apply for Special Consideration in respect of a final unit grade, where their achievement was affected by Exceptional Circumstances as set out in the Assessment, Examination and Moderation Procedures - for more information visit https://askus2.ecu.edu.au/s/article/000003318.

ENS2456|2|1

School: Engineering

This unit information may be updated and amended immediately prior to semester. To ensure you have the correct outline, please check it again at the beginning of semester.

Your unit may be subject to government or third party COVID-19 vaccination requirements. Please consider this before enrolling in this unit, and speak with the unit coordinator if this raises any concerns.

  • Unit Title

    Digital Electronics
  • Unit Code

    ENS2456
  • Year

    2022
  • Enrolment Period

    2
  • Version

    3
  • Credit Points

    15
  • Full Year Unit

    N
  • Mode of Delivery

    On Campus
    Online
  • Unit Coordinator

    Dr Yamaan Esmiel Majeed AL-SHAMMARI

Description

This unit presents a technology review of digital logic families. Memory functions, memory types, and the design of large memory arrays are explained and an introduction to FPGA and CPLB programmable logic devices is given. Digital design and analysis methods, top-down design, algorithmic state machines (ASM), synthesis of ASM, sequencing and control and CPU design are also covered. An introduction to VHDL, simulation and testing of digital systems is included.

Equivalent Rule

Unit was previously coded ENS2256

Learning Outcomes

On completion of this unit students should be able to:

  1. Analyse and design simple CPU.
  2. Describe digital logic in VHDL language.
  3. Describe digital systems as algorithmic state machines and synthesize ASM.
  4. Design a test for digital system.
  5. Use modern engineering design environment.
  6. Use the building blocks of digital systems, including programmable logic devices.

Unit Content

  1. Algorithmic state machines (ASM); synthesis of ASM.
  2. Digital design and analysis methods; top-down design.
  3. Digital logic families technology review.
  4. Engineering design environment.
  5. Introduction to VHDL.
  6. Memory as major component of digital systems memory types, large memory arrays.
  7. Programmable logic devices FPGA, CPLB.
  8. Sequencing and control; design of CPU.
  9. Simulation and testing of digital systems.
  10. VHDL description of combinational and sequential logic.

Assessment

GS1 GRADING SCHEMA 1 Used for standard coursework units

Students please note: The marks and grades received by students on assessments may be subject to further moderation. All marks and grades are to be considered provisional until endorsed by the relevant School Progression Panel.

ON CAMPUS
TypeDescriptionValue
TestIn class tests30%
ReportLaboratory reports20%
Examination ^End of semester examination50%
ONLINE
TypeDescriptionValue
AssignmentOpen book take home test with viva component30%
ReportVirtual laboratory reports20%
Assignment ^Summative assessment of unit content50%

^ Mandatory to Pass


Disability Standards for Education (Commonwealth 2005)

For the purposes of considering a request for Reasonable Adjustments under the Disability Standards for Education (Commonwealth 2005), inherent requirements for this subject are articulated in the Unit Description, Learning Outcomes and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the support for students with disabilities or medical conditions can be found at the Access and Inclusion website.

Academic Integrity

Integrity is a core value at Edith Cowan University, and it is expected that ECU students complete their assessment tasks honestly and with acknowledgement of other people's work. This means that assessment tasks must be completed individually (unless it is an authorised group assessment task) and any sources used must be referenced.

Breaches of academic integrity can include:

Plagiarism

Copying the words, ideas or creative works of other people, without referencing in accordance with stated University requirements. Students need to seek approval from the Unit Coordinator within the first week of study if they intend to use some of their previous work in an assessment task (self-plagiarism).

Unauthorised collaboration (collusion)

Working with other students and submitting the same or substantially similar work or portions of work when an individual submission was required. This includes students knowingly providing others with copies of their own work to use in the same or similar assessment task(s).

Contract cheating

Organising a friend, a family member, another student or an external person or organisation (e.g. through an online website) to complete or substantially edit or refine part or all of an assessment task(s) on their behalf.

Cheating in an exam

Using or having access to unauthorised materials in an exam or test.

Serious outcomes may be imposed if a student is found to have committed one of these breaches, up to and including expulsion from the University for repeated or serious acts.

ECU's policies and more information about academic integrity can be found on the student academic integrity website.

All commencing ECU students are required to complete the Academic Integrity Module.

Assessment Extension

In some circumstances, Students may apply to their Unit Coordinator to extend the due date of their Assessment Task(s) in accordance with ECU's Assessment, Examination and Moderation Procedures - for more information visit https://askus2.ecu.edu.au/s/article/000001386.

Special Consideration

Students may apply for Special Consideration in respect of a final unit grade, where their achievement was affected by Exceptional Circumstances as set out in the Assessment, Examination and Moderation Procedures - for more information visit https://askus2.ecu.edu.au/s/article/000003318.

ENS2456|3|2